Name
Title | ||
|---|---|---|
A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH Δ Σ Modulator Dissipating 16 mW Power. |
Abstract | ||
|---|---|---|
This paper presents a new stage-sharing technique in a discrete-time (DT) 2-2 MASH delta-sigma (ΔΣ) ADC to reduce the modulator power consumption and chip die area. The proposed technique shares all active blocks between the two stages of the modulator. The 2-2 MASH modulator utilizes the second-order Chain of Integrators with Weighted Feed-forward Summation (CIFF) and the Cascade of Integrators w... |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TCSI.2012.2206509 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | Field | DocType |
Modulation,Multi-stage noise shaping,Clocks,Adders,Noise,Power demand,Bandwidth | Electronic engineering,Modulation,Bandwidth (signal processing),Mathematics | Journal |
Volume | Issue | ISSN |
59 | 8 | 1549-8328 |
Citations | PageRank | References |
12 | 0.73 | 5 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ramin Zanbaghi | 1 | 19 | 5.18 |
| Saurabh Saxena | 2 | 174 | 16.84 |
| Gabor C. Temes | 3 | 211 | 57.86 |
| Terri S. Fiez | 4 | 167 | 47.25 |