Name
Abstract | ||
|---|---|---|
While estimating glitches or spurious transitions is a challenge due to signal correlations, the random behavior of logic gate delays makes the estimation problem even more difficult. In this paper, we present statistical estimation of signal activity at the internal and output nodes of combinational Complementary Metal-Oxide-Semiconductor (CMOS) logic circuits considering uncertainty of gate delays. The methodology is based on the stochastic models of logic signals and the probabilistic behavior of gate delays due to process variations, interconnect parasitics, etc. We propose a statistical technique of estimating average-case activity, which is exible in adopting different delay models and variations and can be integrated with worst-case analysis into statistical logic design process. Experimental results show that the uncertainty of gate delays has a great impact on activity at individual nodes (more than 100%) and total power dissipation (can be overestimated up to 65%) as well. |
Year | Venue | Keywords |
|---|---|---|
1998 | Integrated Computer-Aided Engineering | statistical estimation,gate delay,signal activity,logic signal,average-case activity,estimation problem,statistical logic design process,uncertain delays,power estimation,statistical technique,logic gate delay,logic circuit |
Field | DocType | Volume |
Delay calculation,Logic synthesis,Logic gate,Sequential logic,Control theory,CMOS,Stochastic modelling,Probabilistic logic,Engineering,Spurious relationship | Journal | 5 |
Issue | ISSN | Citations |
2 | 1069-2509 | 0 |
PageRank | References | Authors |
0.34 | 16 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tan-Li Chou | 1 | 181 | 23.80 |
| Kaushik Roy | 2 | 7093 | 822.19 |