Paper Info
Title
Optimizing Communication And Capacity In A 3d Stacked Reconfigurable Cache Hierarchy
Abstract
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper we postulate a 3D chip design that stacks SRAM and DRAM upon processing cores and employs OS-based page coloring to minimize horizontal communication of cache data. We then propose a heterogeneous reconfigurable cache design that takes advantage of the high density of DRAM and the superior power/delay characteristics of SRAM to efficiently, meet the working set demands of each individual core. Finally, we analyze the communication patterns for such a processor and show that a tree topology is an ideal fit that significantly reduces the power and latency requirements of the on-chip network. The above proposals art, synergistic: each proposal is made more compelling because of its combination with the other innovations described in this paper The proposed reconfigurable cache model improves performance by up to 19% along with 48% savings in network power.
Year
DOI
Venue
2009
10.1109/HPCA.2009.4798261
HPCA-15 2009: FIFTEENTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS
Keywords
Field
DocType
multi-core processors, cache and memory hierarchy, non-uniform cache architecture (NUCA), page coloring, on-chip networks, SRAM/DRAM cache reconfiguration
Pipeline burst cache,Computer architecture,Cache invalidation,Cache pollution,Cache,Computer science,Parallel computing,Page cache,Cache algorithms,Real-time computing,Cache coloring,Smart Cache
Conference
ISSN
Citations 
PageRank 
1530-0897
41
1.77
References 
Authors
31
8
Name
Order
Citations
PageRank
Niti Madan12279.43
Li Zhao260434.84
Naveen Muralimanohar3129557.58
Aniruddha N. Udipi41505.94
Rajeev Balasubramonian52302116.79
Ravishankar Iyer672035.52
Srihari Makineni760037.89
Donald Newell8411.77