Name
Title | ||
|---|---|---|
A sub-0.75°RMS-phase-error differentially-tuned fractional-N synthesizer with on-chip LDO regulator and analog-enhanced AFC technique. |
Abstract | ||
|---|---|---|
This paper presents a low-phase-error wideband fractional-N frequency synthesizer. Differential tuning is described and a level shift circuit is proposed to obtain symmetrical tuning range. On-chip LDO regulator is designed to improve the power supply rejection for VCO. A voltage monitor is used to enhance the digital AFC technique to overcome the temperature variation. The synthesizer was implemented in a 0.18-μm CMOS process with a 16-mA supply current and a 1.47-mm2 die area. The measured in-band phase noise is less than -97 dBc/Hz at a 10-kHz frequency offset and the integrated phase error is less than 0.75°RMS. The measured reference spur is less than -71 dBc and the locking time is smaller than 20 μs. © 2009 IEEE. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/CICC.2009.5280924 | CICC |
Keywords | DocType | Volume |
null | Conference | null |
Issue | Citations | PageRank |
null | 0 | 0.34 |
References | Authors | |
1 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lei Lu | 1 | 164 | 21.93 |
| Lingbu Meng | 2 | 0 | 0.34 |
| Liang Zou | 3 | 143 | 12.73 |
| Hao Min | 4 | 57 | 5.09 |
| Zhangwen Tang | 5 | 52 | 8.89 |