Name
Abstract | ||
|---|---|---|
The need for higher data rates is ever rising as wireless communications standards move from the third to the fourth generation. Turbo-Codes are the prevalent channel codes for wireless systems due to their excellent forward error correction capability. So far research has mainly focused on components of high throughput Turbo-Decoders. In this paper we explore the Turbo-Decoder design space anew, both under system design and deep-submicron implementation aspects.Our approach incorporates all levels of design, from I/O behavior down to floorplaning taking deep-submicron effects into account. Its scalability allows to derive optimized architectures tailored to the given throughput and target technology. We present results for 3GPP compliant Turbo-Decoders beyond 100 Mbit/s synthesized on a 0.18 μm standard cell library. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1023/B:VLSI.0000047272.75049.0e | VLSI Signal Processing |
Keywords | DocType | Volume |
Turbo-Decoder,high-throughput,wireless,parallel decoding,interleaving,VLSI architectures | Journal | 39 |
Issue | ISSN | Citations |
1-2 | 0922-5773 | 31 |
PageRank | References | Authors |
2.91 | 11 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michael J. Thul | 1 | 67 | 7.24 |
| Frank Gilbert | 2 | 55 | 5.88 |
| Timo Vogt | 3 | 77 | 8.09 |
| Gerd Kreiselmaier | 4 | 38 | 3.66 |
| Norbert Wehn | 5 | 1165 | 137.17 |