Paper Info
Title
An Architecture to Enable Life Cycle Testing in CMPs
Abstract
CMOS wear-out mechanisms such as time dependent breakdown of gate dielectrics (TDDB), hot carrier injection (HCI), negative bias temperature instability (NBTI), electro migration (EM), and stress induced voiding (SIV) are well documented in the literature. Often the onset of wear-out is gradual, with initial manifestation as delay defects that result in timing errors. This motivates the need for online testing. The combined effect of dynamic reconfiguration such as voltage and frequency scaling (DVFS) and signal integrity issues coupled with aging related wear-outs complicate a priori selection of test vectors, further favoring online testing. Traditional online test techniques such as Double and Triple Modular Redundancy (DMR and TMR) pose severe area and power overheads. In this paper we propose an architecture to assist online testing in a Chip Multiprocessor (CMP) based on execution path recording. Since in practice, core utilization in CMPs is low, we can use the idle time of cores opportunistically to run test threads that mimic functional threads. The initiation, termination and comparison of test results is performed by a dedicated, simple and functionally limited small core that we call the Sentry Core (SC). The sentry core is hidden from the OS and has the ability to monitor and interrupt the general-purpose cores. Upon interrupt, the general-purpose core can send data to the sentry core. To detect errors, the SC initializes the general-purpose cores and collects signatures from hardware monitors (that compact execution traces) and compares them against duplicate test threads, obviating any need for cycle by cycle comparison. Major benefits of the proposed solution include: (1) online testing with minimal area overhead, (2) scalability, and (3) testability throughout the life cycle of a CMP. Experimental results show that the proposed scheme is capable of detecting 87% of the faults injected into the processor at an area overhead of less than 3% of the target CMP.
Year
DOI
Venue
2011
10.1109/DFT.2011.26
DFT
Keywords
Field
DocType
enable life cycle testing,test thread,test vector,test result,sentry core,core utilization,traditional online test technique,general-purpose core,duplicate test thread,online testing,functionally limited small core,hot carriers,error detection,fault detection,life cycle,electromigration,signal integrity,wear,negative bias temperature instability
Interrupt,Testability,Computer science,Signal integrity,Triple modular redundancy,Thread (computing),Real-time computing,Multiprocessing,Electronic engineering,Frequency scaling,Control reconfiguration,Embedded system
Conference
ISSN
Citations 
PageRank 
1550-5774
4
0.42
References 
Authors
17
3
Name
Order
Citations
PageRank
R. Rodrigues111110.56
Israel Koren21579175.07
Sandip Kundu31103137.18