Paper Info
Title
Design of a Robust 8-Bit Microprocessor to Soft Errors
Abstract
This work presents a fault-tolerant version of the mass-produced 8-bit microprocessor M68HC11. It is able to tolerate Single Event Transients (SETs) and Single Event Upsets (SEUs). Based on Triple Modular Redundancy (TMR) and Time Redundancy (TR) fault tolerance techniques, a protection scheme was implemented at high level in the sensitive areas of the microprocessor by using only standard gates in order to save design time. Furthermore, fault-tolerant IC design issues and results in area and performance were compared with a non-protected microprocessor version.
Year
DOI
Venue
2006
10.1109/IOLTS.2006.21
Lake Como
Keywords
Field
DocType
soft errors,robust 8-bit microprocessor,8-bit microprocessor,single event transients,time redundancy,triple modular redundancy,non-protected microprocessor version,design time,single event upsets,fault tolerance technique,fault-tolerant version,fault-tolerant ic design issue,logic design,set,redundancy,fault tolerant,logic gates,8 bit,soft error,integrated circuit design
Logic synthesis,Logic gate,Computer science,Microprocessor,8-bit,Triple modular redundancy,Real-time computing,Integrated circuit design,Fault tolerance,Redundancy (engineering),Embedded system
Conference
ISBN
Citations 
PageRank 
0-7695-2620-9
5
0.49
References 
Authors
3
3
Name
Order
Citations
PageRank
Rodrigo Possamai Bastos18013.80
Fernanda Lima Kastensmidt255461.82
Ricardo Reis324928.56