Name
Title | ||
|---|---|---|
A diagnosis method for single logic design errors in gate-level combinational circuits. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1002/(SICI)1520-684X(19970615)28:6<30::AID-SCJ4>3.0.CO;2-N | Systems and Computers in Japan |
Keywords | Field | DocType |
logic design,combinational circuit | Logic synthesis,Logic gate,Pattern generation,Computer science,Algorithm,Circuit design,Combinational logic,Electronic circuit,Design Error | Journal |
Volume | Issue | Citations |
28 | 6 | 0 |
PageRank | References | Authors |
0.34 | 8 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Atsushi Yoshikawa | 1 | 0 | 0.34 |
| Seiji Kajihara | 2 | 989 | 73.60 |
| Masahiro Numa | 3 | 82 | 20.87 |
| Kozo Kinoshita | 4 | 756 | 118.08 |