Name
Abstract | ||
|---|---|---|
A MOS transistor-array structure for accurate subthreshold current characterization is presented. Two architectural improvements called LCS and PES, and measured data treatment called MCC are utilized. The LCS, leakage current cut-off switch, reduces unwanted leakage current of the non-target devices which masks the target leakage current. The PES, potential equalizing supply, further reduces the ... |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/JSSC.2009.2028944 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
MOSFETs,Leakage current,Current measurement,Subthreshold current,Circuit testing,Switches,Random access memory,Circuit optimization,Threshold voltage,Large scale integration | Array data structure,Transistor array,Leakage (electronics),Current source,Computer science,Electronic engineering,Subthreshold conduction,MOSFET,Transistor,Threshold voltage,Electrical engineering | Journal |
Volume | Issue | ISSN |
44 | 11 | 0018-9200 |
Citations | PageRank | References |
2 | 0.54 | 6 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Takashi Sato | 1 | 81 | 36.76 |
| Hiroyuki Ueyama | 2 | 16 | 1.68 |
| Noriaki Nakayama | 3 | 30 | 8.95 |
| Kazuya Masu | 4 | 120 | 36.37 |