Name
Abstract | ||
|---|---|---|
Sub-threshold static and ratioed logic have recently been proposed to satisfy the ultra-low power requirement in applications such as hearing aid, pace-maker, wearable wrist-watch computer etc. These logic circuits, however, can be operated only at lower frequencies due to lower supply voltage. To increase the frequency of operation, we propose sub-threshold dynamic logic: Sub-Domino logic. A standard full-adder circuit is implemented in both Sub-Domino and Sub-CMOS logic operating in the subthreshold region. Simulation results show that Sub-Domino logic has lower power consumption, smaller area (60% of Sub-CMOS logic), and is 3 times faster than Sub-CMOS logic. It is also shown that Sub-Domino logic has excellent noise margin. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/ICVD.2001.902662 | VLSI Design |
Keywords | Field | DocType |
ultra-low power dynamic sub-threshold,digital logic,sub-threshold dynamic logic,lower power consumption,ratioed logic,sub-domino logic,sub-cmos logic operating,ultra-low power requirement,sub-cmos logic,lower frequency,lower supply voltage,logic circuit,adders,frequency,voltage,wearable computers,noise margin,low power electronics,area,logic circuits,computational modeling,dynamic logic,satisfiability,application software | Domino logic,Logic gate,Sequential logic,Pass transistor logic,Logic optimization,Computer science,Electronic engineering,Real-time computing,Logic level,Dynamic logic (digital electronics),Logic family,Electrical engineering | Conference |
ISBN | Citations | PageRank |
0-7695-0831-6 | 10 | 1.12 |
References | Authors | |
4 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| hendrawan soeleman | 1 | 258 | 62.61 |
| Kaushik Roy | 2 | 7093 | 822.19 |
| Bipul Paul | 3 | 19 | 5.47 |