Title
1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters
Abstract
This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, we employed the I/Q amplifier sharing technique [1] in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24 mW/ch from a 1.2-V power supply. The measured SNR and SNDR are 58.6 dB and 52.2 dB, respectively.
Year
DOI
Venue
2008
10.1093/ietfec/e91-a.2.454
IEICE Transactions
Keywords
Field
DocType
90-nm cmos technology,power reduction,conversion stage,q amplifier sharing technique,common-mode disturbance,proposed common-mode feedforward,q channel,power supply,power consumption,d converter,d converters,common source
Communication channel,Converters,CMOS,Theoretical computer science,Electrical engineering,Mathematics,Feed forward,Amplifier,Embedded system,Power consumption
Journal
Volume
Issue
ISSN
E91-A
2
0916-8508
Citations 
PageRank 
References 
2
0.60
4
Authors
5
Name
Order
Citations
PageRank
Takeshi Ueno1204.27
Tomohiko Ito2164.40
Daisuke Kurose3175.11
Takafumi Yamaji45518.00
Tetsuro Itakura518733.44