Name
Abstract | ||
|---|---|---|
This paper introduces a new bounded multi-level algebraic form, called Projected Sum of Products (P-SOP), based on projections of minimal SOP forms onto subsets of the Boolean space. After a standard two-level logic minimization, this technique can be used as a very fast postprocessing step for further minimizing the circuit area, increasing the depth of the network by only a constant value. The proposed synthesis algorithms have been implemented and tested with interesting results, which show how about 75% of standard Espresso benchmarks benefit from this postprocessing phase. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/DSD.2008.105 | DSD |
Keywords | Field | DocType |
standard espresso benchmarks,minimal sop form,projected sum,postprocessing step,constant value,circuit area,postprocessing phase,interesting result,boolean space,standard two-level logic minimization,benchmark testing,logic gates,sum of products,data structures,boolean algebra,boolean functions,logic synthesis | Logic synthesis,Boolean function,Espresso,Canonical normal form,Logic gate,Computer science,Algorithm,Minification,Boolean algebra,Bounded function | Conference |
Citations | PageRank | References |
5 | 0.65 | 12 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Anna Bernasconi | 1 | 173 | 26.93 |
| Valentina Ciriani | 2 | 422 | 35.11 |
| Roberto Cordone | 3 | 310 | 28.87 |