Name
Abstract | ||
|---|---|---|
In this paper, we study circuits implemented using high-density arrays composed of Vertical Slit Field Effect Transistors. This layout style could dramatically increase transistor density and therefore reduce fabrication cost. However, its geometrical restrictions, imposed by the super-regular transistor arrangement and strictly parallel metal tracks pose new design challenges. Our experiments reveal that very dense cell-level interconnect pattern may be responsible for unnecessary 15% increase of the circuit-level, critical path delays. We demonstrate that these extra delays can be avoided by constructing appropriate cell interconnect layouts and by more flexible usage of available metal layers for intra-cell routing. To balance the performance and metal layer usage, we propose a linear programming-based technique for critical net re-routing. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1735023.1735062 | ISPD |
Keywords | Field | DocType |
super-regular transistor arrangement,high-density regular circuit,metal layer usage,flexible usage,dense cell-level,critical path delay,appropriate cell,transistor density,parallel metal track,available metal layer,performance study,vertical slit field effect,critical path,dfm,field effect transistor,linear program | Mathematical optimization,Computer science,Field-effect transistor,Electronic engineering,Linear programming,Critical path method,Transistor,Electronic circuit,Interconnection,Design for manufacturability,Fabrication | Conference |
Citations | PageRank | References |
1 | 0.39 | 10 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yi-wei Lin | 1 | 52 | 5.22 |
| Malgorzata Marek-Sadowska | 2 | 2272 | 213.72 |
| Wojciech Maly | 3 | 1976 | 352.57 |