Name
Title | ||
|---|---|---|
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation |
Abstract | ||
|---|---|---|
This paper considers the problem of testing VLSI integrated circuits without exceeding their power ratings during test. The proposed approach is based on the reordering of test vectors of a given test sequence to minimize the average and peak power dissipation during test operation. For this purpose, the proposed technique reduces the internal switching activity by lowering the transition density at circuit inputs. The technique considers combinational or full scan sequential circuits and do not modify the initial fault coverage. Results of experiments show reductions of the switching activity ranging from 11 % to 66 % during external test application. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/GLSV.1999.757369 | Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
test vector,test operation,vlsi integrated circuit,power rating,proposed technique,internal switching activity,test vector ordering technique,peak power dissipation,external test application,switching activity reduction,test sequence,robots,very large scale integration,automatic test pattern generation,fault coverage,sequential circuits,vlsi,integrated circuit,power dissipation,combinational circuits,nondestructive testing,test | Automatic test pattern generation,Test vector,Sequential logic,Fault coverage,Computer science,Real-time computing,Electronic engineering,Combinational logic,Test compression,Very-large-scale integration,Integrated circuit | Conference |
ISSN | ISBN | Citations |
1066-1395 | 0-7695-0104-4 | 23 |
PageRank | References | Authors |
1.31 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| P. Girard | 1 | 478 | 41.91 |
| L. Guiller | 2 | 380 | 24.24 |
| C. Landrault | 3 | 93 | 31.86 |
| S. Pravossoudovitch | 4 | 689 | 54.12 |