Title
An Error Control Code Scheme for Multilevel Flash Memories
Abstract
Abstract: This paper presents a new scheme for error control coding in multilevel Flash memories. The n bits stored in a single memory cell are organized in different "bit-layers", which are independent from one another. Error correction is carried out separately for each bit-layer. The correction of any failure in a single memory cell is therefore achieved by using a simple error control code (ECC) providing single-bit correction, regardless of the number of bits stored in a single cell. This greatly simplifies the encoding and decoding circuits and minimizes the impact of ECC time overhead on memory access time. Moreover the same encoding/decoding circuit and check cells are used with multilevel memories working at a variable number of bits per cell.
Year
DOI
Venue
2001
10.1109/MTDT.2001.945227
MTDT
Keywords
Field
DocType
error correction,error control,single-bit correction,simple error control code,multilevel memory,multilevel flash memories,decoding circuit,single cell,error control code scheme,memory access time,single memory cell,multilevel flash memory,circuits,decoding,fabrication,encoding,nonvolatile memory,block codes,threshold voltage
Flash memory,Access time,Computer science,Block code,Parallel computing,Error detection and correction,Non-volatile memory,Decoding methods,Computer hardware,Encoding (memory),Memory cell
Conference
ISSN
Citations 
PageRank 
1087-4852
3
1.01
References 
Authors
2
4
Name
Order
Citations
PageRank
Stefano Gregori16224.34
Guido Torelli224064.39
Osama Khouri34114.44
Rino Micheloni46912.85