A Novel Graph Expansion and a Decoding Algorithm for NB-LDPC Codes | 0 | 0.34 | 2020 |
Coset Probability Based Majority-logic Decoding for Non-binary LDPC Codes | 0 | 0.34 | 2019 |
Efficient Decoding Of Low Density Lattice Codes | 0 | 0.34 | 2019 |
Enabling Computational Storage Through FPGA Neural Network Accelerator for Enterprise SSD. | 0 | 0.34 | 2019 |
LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives | 1 | 0.37 | 2019 |
Fast Decoding of Low Density Lattice Codes. | 0 | 0.34 | 2018 |
Array Architectures for 3-D NAND Flash Memories. | 4 | 0.93 | 2017 |
Solid-State Drive (SSD): A Nonvolatile Storage System. | 0 | 0.34 | 2017 |
Solid-State Drives (SSDs) [Scanning the Issue]. | 0 | 0.34 | 2017 |
Architectural And Integration Options For 3d Nand Flash Memories | 0 | 0.34 | 2017 |
Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance. | 0 | 0.34 | 2017 |
Design space exploration of latency and bandwidth in RRAM-based solid state drives | 0 | 0.34 | 2015 |
SSDExplorer: a Virtual Platform for Performance/Reliability-oriented Fine-Grained Design Space Exploration of Solid State Drives | 4 | 0.47 | 2015 |
SSDExplorer: a virtual platform for fine-grained design space exploration of solid state drives | 3 | 0.49 | 2014 |
Overclocking nand Flash Memory I/O Link in LDPC-Based SSDs | 4 | 0.46 | 2014 |
3-D Data Storage, Power Delivery, and RF/Optical Transceiver—Case Studies of 3-D Integration From System Design Perspectives | 11 | 1.01 | 2009 |
Non-Volatile Memories for Removable Media | 14 | 1.29 | 2009 |
A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput | 19 | 1.92 | 2006 |
An Error Control Code Scheme for Multilevel Flash Memories | 3 | 1.01 | 2001 |
Low Output Resistance Charge Pump for Flash Memory Programming | 1 | 0.36 | 2001 |
Fast Voltage Regulator for Multilevel Flash Memories | 2 | 0.44 | 2000 |
Hierarchical Sector Biasing Organization for Flash Memories | 3 | 0.71 | 2000 |