Name
Affiliation
Papers
RINO MICHELONI
Qimonda Flash GmbH, Munich
22
Collaborators
Citations 
PageRank 
57
69
12.85
Referers 
Referees 
References 
195
255
55
Search Limit
100255
Title
Citations
PageRank
Year
A Novel Graph Expansion and a Decoding Algorithm for NB-LDPC Codes00.342020
Coset Probability Based Majority-logic Decoding for Non-binary LDPC Codes00.342019
Efficient Decoding Of Low Density Lattice Codes00.342019
Enabling Computational Storage Through FPGA Neural Network Accelerator for Enterprise SSD.00.342019
LDPC Soft Decoding with Improved Performance in 1X-2X MLC and TLC NAND Flash-Based Solid State Drives10.372019
Fast Decoding of Low Density Lattice Codes.00.342018
Array Architectures for 3-D NAND Flash Memories.40.932017
Solid-State Drive (SSD): A Nonvolatile Storage System.00.342017
Solid-State Drives (SSDs) [Scanning the Issue].00.342017
Architectural And Integration Options For 3d Nand Flash Memories00.342017
Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance.00.342017
Design space exploration of latency and bandwidth in RRAM-based solid state drives00.342015
SSDExplorer: a Virtual Platform for Performance/Reliability-oriented Fine-Grained Design Space Exploration of Solid State Drives40.472015
SSDExplorer: a virtual platform for fine-grained design space exploration of solid state drives30.492014
Overclocking nand Flash Memory I/O Link in LDPC-Based SSDs40.462014
3-D Data Storage, Power Delivery, and RF/Optical Transceiver—Case Studies of 3-D Integration From System Design Perspectives111.012009
Non-Volatile Memories for Removable Media141.292009
A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput191.922006
An Error Control Code Scheme for Multilevel Flash Memories31.012001
Low Output Resistance Charge Pump for Flash Memory Programming10.362001
Fast Voltage Regulator for Multilevel Flash Memories20.442000
Hierarchical Sector Biasing Organization for Flash Memories30.712000