Name
Abstract | ||
|---|---|---|
Time predictability is one of the most important design considerations for real-time systems. In this article, we study the impact of instruction prefetching on the worst-case performance of instruction caches. We extend the static cache simulation technique to model and compute the worst-case instruction cache performance with prefetching. The evaluation results show that instruction prefetching can benefit both the average-case and worst-case performance; however, the degree of the worst-case performance improvement due to instruction prefetching is less than that of the average-case performance. As a result, the time variation of computing is increased by instruction prefetching. Also, our experimental results indicate that the prefetching distance can significantly impact the worst-case performance of instruction caches with instruction prefetching. Specifically, when the prefetching distance is equal to the L1 miss penalty, the worst-case execution time with instruction prefetching is minimized. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1457246.1457253 | ACM Transactions on Embedded Computing Systems (TECS) |
Keywords | Field | DocType |
instruction prefetching,time variation,hard real-time,worst-case execution time,worst-case performance improvement,instruction caches,prefetching distance,average-case performance,worst-case instruction cache performance,worst-case execution time analysis,worst-case performance,time predictability,instruction cache,real time systems,worst case execution time | Predictability,Worst-case execution time,Cache,Computer science,Parallel computing,Real-time computing,Execution time,Performance improvement | Journal |
Volume | Issue | ISSN |
8 | 1 | 1539-9087 |
Citations | PageRank | References |
1 | 0.35 | 23 |
Authors | ||
2 | ||