Name
Abstract | ||
|---|---|---|
We propose a novel energy-efficient cache architecture based on a matching mechanism that uses a reduced number of tag bits. The idea behind the proposed architecture is based on moving a large subset of the tag bits from the cache into an external register (called the Tag Overflow Buffer) that serves as an identifier of the current locality of the memory references. Dynamic energy efficiency is achieved by accessing, for most of the memory references, a reduced-tag cache; furthermore, because of the reduced number of tag bits, leakage energy is also reduced as a by-product. We achieve average energy savings ranging from 16% to 40% (depending on different cache structural parameters) on total (i.e., static and dynamic) cache energy, and measured on a standard suite of embedded applications. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/TVLSI.2009.2016720 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
total memory energy,tag bit,reduced number,different cache structural parameter,tag overflow buffering,memory reference,leakage energy,cache energy,reduced-tag cache,average energy saving,novel energy-efficient cache architecture,reduced-tag matching,dynamic energy efficiency,embedded system,energy efficient,energy efficiency,hardware,cache memory,circuits,low power electronics,registers,structural engineering | Tag RAM,Cache invalidation,Cache pollution,Cache,Computer science,Parallel computing,Cache-only memory architecture,Real-time computing,Page cache,Cache algorithms,Cache coloring | Journal |
Volume | Issue | ISSN |
17 | 5 | 1063-8210 |
Citations | PageRank | References |
3 | 0.39 | 12 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mirko Loghi | 1 | 218 | 17.83 |
| Paolo Azzoni | 2 | 30 | 4.18 |
| Massimo Poncino | 3 | 125 | 18.57 |