Title
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations
Abstract
A Network-on-Chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected through programmable crosspoints. Since an NoC may provide a number of paths between a given source and destination, manufacturing or runtime faults on one interconnect does not necessarily render the chip useless. It is partly because of this fault tolerance that NoCs have emerged as a viable alternative for implementing communication between functional units of a chip in the nanometer regime, where high defect rates are prevalent. In this paper, we quantify the fault tolerance offered by an NoC against process variations. Specifically, we develop an analytical model for the probability of failure in buffered global NoC links due to interconnect dishing, and effective channel length variation. Using the developed probability model, we study the impact of link failure on the number of cycles required to establish communications in NoC applications.
Year
DOI
Venue
2007
10.1109/ISQED.2007.129
ISQED
Keywords
Field
DocType
developed probability model,analytical model,provisioning on-chip networks,point-to-point interconnects,buffered rc interconnect delay,noc application,link failure,buffered global noc,runtime fault,on-chip communication,fault tolerance,shared interconnects,process variation,cmos technology,network on a chip,fault tolerant,chip,hardware,network on chip,planarization,surface resistance,functional unit,point to point
Probability model,Computer science,Probability of failure,Network on a chip,Communication channel,Provisioning,Real-time computing,Chip,Electronic engineering,Fault tolerance,Interconnection,Embedded system
Conference
ISBN
Citations 
PageRank 
0-7695-2795-7
22
0.91
References 
Authors
6
5
Name
Order
Citations
PageRank
Mosin Mondal1865.93
Tamer Ragheb226618.65
Xiang Wu3221.25
Adnan Aziz41778149.76
Yehia Massoud5772113.05