Name
Abstract | ||
|---|---|---|
Growth in floating-point applications for field-programmable gate arrays (FPGAs) has made it critical to optimize floating-point units for FPGA technology. The divider is of particular interest because the design space is large and divider usage in applications varies widely. Obtaining the right balance between clock speed, latency, throughput, and area in FPGAs can be challenging. The designs presented here cover a range of performance, throughput, and area constraints. On a Xilinx Virtex4-11 FPGA, the range includes 250-MHz IEEE compliant double precision divides that are fully pipelined to 187-MHz iterative cores. Similarly, area requirements range from 4100 slices down to a mere 334 slices. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/TVLSI.2007.891099 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
divider usage,floating-point unit,floating-point application,design space,ieee compliant double precision,fpga technology,area requirement,area constraint,floating-point divider design,clock speed,187-mhz iterative core,ieee 754,logic design,field programmable gate array,floating point arithmetic,floating point,floating point unit,field programmable gate arrays | Logic synthesis,Computer science,Floating point,Double-precision floating-point format,Field-programmable gate array,Electronic engineering,Throughput,Computer hardware,Integrated circuit,Clock rate,IEEE floating point,Embedded system | Journal |
Volume | Issue | ISSN |
15 | 1 | 1063-8210 |
Citations | PageRank | References |
6 | 0.50 | 11 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| K. Scott Hemmert | 1 | 577 | 50.62 |
| Keith D. Underwood | 2 | 847 | 77.39 |