Name
Abstract | ||
|---|---|---|
In this paper, a new method for reducing scan shifts is presented. Scan design is one of the most popular designs for test method for sequential circuits. However, for circuits with many flip-flops, it requires a long test application time and high test-data volume. Our new scan method utilizes two configurations of scan chains, a folding scan tree and a fully compatible scan tree to alleviate these problems. It is observed that uncompacted test patterns typically contain a large fraction of don't care values. This property is exploited in the fully compatible scan tree to reduce scan shifts without degrading fault coverage. Then, a folding scan tree is configured to further reduce the length of scan chain and scan shifts. Experimental results on benchmark circuits show that this scan method can significantly reduce scan shifts. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1007/s10836-005-2719-2 | J. Electronic Testing |
Keywords | Field | DocType |
sequential circuit,design for test,sequential circuits,design for testability,fault coverage | Design for testing,Test method,Sequential logic,Fault coverage,Compatibility (mechanics),Computer science,Scan chain,Electronic engineering,Real-time computing,Test compression,Electronic circuit | Journal |
Volume | Issue | ISSN |
21 | 6 | 0923-8174 |
Citations | PageRank | References |
4 | 0.45 | 9 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroyuki Yotsuyanagi | 1 | 70 | 19.04 |
| Toshimasa Kuchii | 2 | 19 | 2.14 |
| Shigeki Nishikawa | 3 | 4 | 0.45 |
| Masaki Hashizume | 4 | 98 | 27.83 |
| Kozo Kinoshita | 5 | 23 | 1.33 |