Paper Info
Title
Low complexity LDPC code decoders for next generation standards
Abstract
This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards. A complete exploration of the design space spanning from the decoding schedules, the node processing approximations up to the top-level decoder architecture is detailed. According to this search state-of-the-art techniques for a low complexity design have been adopted in order to meet feasible high throughput decoder implementations. An analysis of the standardized codes from the decoder-aware point of view is also given, presenting, for each one, the implementation challenges (multi rates-length codes) and bottlenecks related to the complete coverage of the standards. Synthesis results on a present 65nm CMOS technology are provided on a generic decoder architecture.
Year
DOI
Venue
2007
10.1109/DATE.2007.364613
DATE
Keywords
Field
DocType
top-level decoder architecture,low complexity design,generic decoder architecture,feasible high throughput decoder,design space,dvb-s2 standard,complete coverage,next generation standard,cmos technology,low complexity ldpc code,complete exploration,digital video broadcasting,high throughput,wimax,sparse matrices,wifi,throughput,system on a chip,ldpc code
Low-density parity-check code,Computer science,DVB-S2,Real-time computing,WiMAX,Schedule,Soft-decision decoder,Decoding methods,Throughput,Design space exploration
Conference
ISSN
ISBN
Citations 
1530-1591
978-3-9810801-2-4
26
PageRank 
References 
Authors
1.35
13
9
Name
Order
Citations
PageRank
T. Brack1261.35
M. Alles2261.35
T. Lehnigk-Emden3261.35
F. Kienle4472.87
N. Wehn510310.43
N. E. L'Insalata6261.35
F. Rossi7261.35
Massimo Rovini81019.32
L. Fanucci916717.90