L. Fanucci - Citegraph

Author Info

Name	Affiliation	Papers
L. FANUCCI	IEIIT, National Research Council, Pisa, Italy	26
Collaborators	Citations	PageRank
89	167	17.90
Referers	Referees	References
431	398	158

Search Limit

100431

Publications (26 rows)

Collaborators (89 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A High Linearity Driver with Embedded Interleaved Track-and-Hold Array for High-Speed ADC	0	0.34	2021
A startup circuit for even-stage differential ring oscillators	0	0.34	2020
Advantages and Limitations of Fully on-Chip CNN FPGA-Based Hardware Accelerator	0	0.34	2020
A simulated approach to evaluate side-channel attack countermeasures for the Advanced Encryption Standard.	0	0.34	2019
Analog-CMDA based interfaces for MEMS gyroscopes	0	0.34	2014
Sensing Devices and Sensor Signal Processing for Remote Monitoring of Vital Signs in CHF Patients	32	1.76	2013
Batteries and battery management systems for electric vehicles	24	3.01	2012
Low-error digital hardware implementation of artificial neuron activation functions and their derivative	12	0.97	2011
Shock immunity enhancement via resonance damping in gyroscopes for automotive applications	0	0.34	2009
Low-g accelerometer fast prototyping for automotive applications	4	0.71	2007
Low complexity LDPC code decoders for next generation standards	26	1.35	2007
ASIP design and synthesis for non linear filtering in image processing	4	0.40	2006
High-precision LDPC codes decoding at the lowest complexity	4	0.56	2006
Dynamic control of motion estimation search parameters for low complex H.264 video coding	10	0.72	2006
Platform based design for automotive sensor conditioning	5	0.83	2005
VLSI Design of a Digital RFI Cancellation Scheme for VDSL Transceivers	0	0.34	2004
A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder	4	0.63	2004
Base Coupled Differential Amplifier: A New Topology For Rf Integrated Lna	0	0.34	2003
A technique for nonlinearity self-calibration of DLLs	0	0.34	2003
VLSI design investigation for low-cost, low-power FFT/IFFT processing in advanced VDSL transceivers	12	0.73	2003
Sensor Platform Design for Automotive Applications	0	0.34	2003
Fast: FFT ASIC automated synthesis	3	0.44	2002
VLSI design for low-power data-adaptive motion estimation	1	0.51	2002
A parametric VLSI architecture for video motion estimation	18	0.93	2001
VLSI implementation of a CDMA blind adaptive interference-mitigating detector	6	0.56	2001
VLSI implementation of a signal recognition and code acquisition algorithm for CDMA packet receivers	2	0.41	1998