Name
Abstract | ||
|---|---|---|
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may use longer time and more power consumption in testing. In this paper, we propose a novel hardware architecture base on "LBIST Controller" to reduce test application time and test power consumption. Give a test cubes for stuck-at faults contain unspecified bit generated by a sequential automatic test pattern generator (ATPG). Use our propose algorithm in section In can group test cubes to several section schemes. Teen mapping to our propose hardware architecture in section II. While "Section Counter" is more then zero, scan in could through MUX and bypass the flip-fiops in "Fixed Group". And we can save power consumption and test application time in this time. According to our simulation result, we reduce about 20%-60% power consumption and 50%-80% test application time in some ISCAS189 benchmarks. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/APCCAS.2006.342207 | 2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS |
Keywords | Field | DocType |
VLSI, testing, DFT, BIST | Automatic test pattern generation,Control theory,Computer science,Digital pattern generator,Electronic engineering,Multiplexer,Very-large-scale integration,Built-in self-test,Hardware architecture,Low-power electronics,Embedded system | Conference |
Citations | PageRank | References |
0 | 0.34 | 10 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jiann-Chyi Rau | 1 | 13 | 6.75 |
| Po-han Wu | 2 | 482 | 31.49 |
| Chia-jung Liu | 3 | 0 | 0.68 |