Name
Abstract | ||
|---|---|---|
This work describes the design of a double-precision radix-8 divider. Low-power techniques are applied in the design of the unit, and energy-delay tradeoffs considered. The energy dissipation in the divider can be reduced by up to 70% with respect to a standard implementation not optimized for energy, without penalizing the latency. The radix-8 divider is compared with the one obtained by overlapping three radix-2 stages and with a radix-4 divider. Results show that the latency of our divider is similar to that of the divider with overlapped stages, but the area is smaller. The speed-up of the radix-8 over the radix-4 is about 20% and the energy dissipated to complete a division is almost the same, although the area of the radix-8 is 50% larger |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/ICCD.1998.727084 | ICCD |
Keywords | Field | DocType |
double-precision radix-8 divider,energy-delay tradeoffs,latency,dividing circuits,custom circuit,small team,digital arithmetic,low-power radix-8 divider,custom datapath circuit technology,ibm austin research laboratory,energy dissipation,gigahertz microprocessor,dynamic array control structure,hardware,lapping | Current divider,Frequency divider,Computer science,Latency (engineering),Dissipation,Real-time computing,Radix,Electronic engineering,Dividing circuits,Wilkinson power divider | Conference |
ISSN | ISBN | Citations |
1063-6404 | 0-8186-9099-2 | 6 |
PageRank | References | Authors |
1.28 | 6 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nannarelli, A. | 1 | 22 | 5.71 |
| Lang, T. | 2 | 6 | 1.28 |