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NANNARELLI, A.
Author Info
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Name
Affiliation
Papers
NANNARELLI, A.
Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA|c|
12
Collaborators
Citations
PageRank
15
22
5.71
Referers
Referees
References
49
119
59
Search Limit
100
119
Publications (12 rows)
Collaborators (15 rows)
Referers (49 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Performance/Power Space Exploration for Binary64 Division Units
4
0.50
2016
Thermal aware floorplanning incorporating temperature dependent wire delay estimation
1
0.35
2015
Characterization of RNS multiply-add units for power efficient DSP
1
0.35
2015
Twenty years of research on RNS for DSP: Lessons learned and future perspectives
0
0.34
2014
Energy efficient FPGA based hardware accelerators for financial applications
2
0.38
2014
Guest Editors’ Introduction: Special Sectionon Computer Arithmetic
0
0.34
2014
Design of power efficient FPGA based hardware accelerators for financial applications
1
0.40
2012
Comments on 'improving the speed of decimal division'
0
0.34
2012
Temperature dependent wire delay estimation in floorplanning.
3
0.41
2011
Radix-16 Combined Division and Square Root Unit
2
0.39
2011
Power-delay tradeoffs in residue number system
2
0.63
2003
Low-power radix-8 divider
6
1.28
1998
1