Title
DAG-Map: graph-based FPGA technology mapping for delay optimization
Abstract
A graph-based technology-mapping package for delay optimization in lookup-table-based field programmable gate array (FPGA) designs is presented. The algorithm, DAG-Map, carries out technology mapping and delay optimization on the entire Boolean network, instead of decomposing it into fan-out-free trees. As a preprocessing phase of DAG-Map, a general algorithm called DMIG, which transforms an arbitrary n-node network into a two-input network with only an O(1) factor increase in network depth, is introduced. A matching-based technique that minimizes area without increasing network delay, and is used in the postprocessing phase of DAG-Map is discussed. DAG-Map is compared with previous FPGA mapping algorithms on a set of logic synthesis benchmarks. The experimental results show that, on average, DAG-Map reduces both network delay and the number of look-up tables.<>
Year
DOI
Venue
1992
10.1109/54.156154
IEEE Design & Test of Computers
Keywords
Field
DocType
preprocessing phase,delay optimization,previous fpga mapping algorithm,lookup-table-based field programmable gate array,network delay,boolean network,two-input network,dmig,logic arrays,general algorithm,logic synthesis benchmarks,delays,graph-based fpga technology mapping,arbitrary n-node network,fan-out-free trees,dag-map,entire boolean network,matching-based technique,postprocessing phase,table lookup,network depth,logic testing,generic algorithm,lookup table,graph matching,logic synthesis
Boolean network,Logic synthesis,Delay calculation,Network delay,Logic optimization,Computer science,Programmable logic array,Algorithm,Electronic engineering,And-inverter graph,Programmable logic device
Journal
Volume
Issue
ISSN
9
3
0740-7475
Citations 
PageRank 
References 
28
2.29
0
Authors
5
Name
Order
Citations
PageRank
Kuang-chien Chen134730.84
Jason Cong27069515.06
Yuzheng Ding323919.46
Andrew B. Kahng47582859.06
Peter Trajmar5352.95