Title
General switch box modeling and optimization for FPGA routing architectures
Abstract
This paper explores the FPGA routing architecture based on a new concept of “general switch box (GSB)” to improve the performance of FPGA. Compared with the existing CB/SB routing architecture and CS-box architecture, the proposed GSB architecture has much larger exploration space. Experimental results with MCNC benchmark circuits show that the performance of FPGAs with GSB is about 24.3% better than the CB/SB architecture with the same segment distribution in terms of product of channel width and delay using 0.17% less routing switches for the single wire length. For the two types of wire segments, we propose an architecture with 13.3% performance improvement at the cost of about 0.8% increase in switch number compared to the single wire length GSB architecture.
Year
DOI
Venue
2010
10.1109/FPT.2010.5681437
FPT
Keywords
Field
DocType
single wire length,network routing,reconfigurable architectures,circuit optimisation,gsb architecture,fpga routing architectures,cb-sb routing architecture,field programmable gate arrays,general switch box modeling,mcnc benchmark circuits,channel width,switches,tin,routing
Routing architecture,Architecture,Switch box,Computer science,Network routing,Field-programmable gate array,Real-time computing,Channel width,Electronic circuit,Performance improvement
Conference
Volume
Issue
ISBN
null
null
978-1-4244-8980-0
Citations 
PageRank 
References 
0
0.34
2
Authors
5
Name
Order
Citations
PageRank
Kejie Ma192.13
Lingli Wang28625.42
Xuegong Zhou3597.12
Sheldon X. -D. Tan482993.06
Jiarong Tong56811.74