Paper Info
Title
Low Latency Pipelined Circular CORDIC
Abstract
Recent research has demonstrated the vulnerability of certain smart card architectures to power and electro-magnetic analysis when multiplier operations areinsufficiently shielded from external monitoring. Here several standard multipliers are investigated ...
Year
DOI
Venue
2005
10.1109/ARITH.2005.30
IEEE Symposium on Computer Arithmetic
Keywords
Field
DocType
multiplier operation,low latency pipelined circular,certain smart card architecture,standard multiplier,external monitoring,electro-magnetic analysis,recent research,adders,computer architecture,graphics,linear approximation,speech processing,vectors,approximation theory,low latency,arithmetic,digital signal processing
Scale factor,Linear approximation,Digital signal processing,Adder,Computer science,Parallel computing,Approximation theory,Theoretical computer science,Multiplication,CORDIC,Latency (engineering)
Conference
ISSN
ISBN
Citations 
1063-6889
0-7695-2366-8
2
PageRank 
References 
Authors
0.39
9
2
Name
Order
Citations
PageRank
Elisardo Antelo126225.04
Julio Villalba221923.56