Name
Abstract | ||
|---|---|---|
This paper presents a unified processor core with two operation modes. The processor core works as a compiler-friendly MIPS-like core in the RISC mode, and it is a 4-way VLIW in its DSP mode, which has distributed and ping-pong register organization optimized for stream processing. To minimize hardware, the DSP mode has no control construct for program flow, while the data manipulation RISC instructions are executed in the DSP datapath. Moreover, the two operation modes can be changed instruction by instruction within a single program stream via the hierarchical instruction encoding, which also helps to reduce the VLIW code sizes significantly. The processor has been implemented in the UMC 0.18um CMOS technology, and its core size is 3.23mmx3.23mm including the 32KB on-chip memory. It can operate at 208MHz while consuming 380.6mW average power. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1145/1057661.1057675 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
vliw dsp,dsp datapath,unified processor core,risc mode,dsp mode,core size,processor core work,data manipulation risc instruction,unified processor architecture,compiler-friendly mips-like core,operation mode,hierarchical instruction encoding,dual core processor,digital signal processor,processor architecture,stream processing,chip | Application-specific instruction-set processor,Digital signal processor,Computer science,Very long instruction word,Real-time computing,Texas Instruments DaVinci,Processor register,Delay slot,Multi-core processor,Microarchitecture | Conference |
ISBN | Citations | PageRank |
1-59593-057-4 | 10 | 0.97 |
References | Authors | |
10 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tay-Jyi Lin | 1 | 139 | 24.36 |
| Chie-min Chao | 2 | 26 | 3.29 |
| Chia-hsien Liu | 3 | 13 | 1.39 |
| Pi-chen Hsiao | 4 | 23 | 2.69 |
| Shin-kai Chen | 5 | 43 | 5.20 |
| Li-Chun Lin | 6 | 13 | 1.73 |
| Chih-Wei Liu | 7 | 158 | 27.02 |
| Chein-Wei Jen | 8 | 588 | 68.52 |