| Latency-Tolerant Virtual Cluster Architecture For Vliw Dsp | 0 | 0.34 | 2007 |
| A 52mW 1200MIPS compact DSP for multi-core media SoC | 0 | 0.34 | 2006 |
| Programmable Fir Filter With Adder-Based Computing Engine | 0 | 0.34 | 2006 |
| PAC DSP Core and Application Processors. | 21 | 1.67 | 2006 |
| An efficient quality-aware memory controller for multimedia platform SoC | 43 | 2.43 | 2005 |
| The Long Length Dht Design With A New Hardware Efficient Distributed Arithmetic Approach And Cyclic Preserving Partitioning | 0 | 0.34 | 2005 |
| Architecture for area-efficient 2-D transform in H.264/AVC | 3 | 0.55 | 2005 |
| Hierarchical instruction encoding for VLIW digital signal processors | 3 | 0.42 | 2005 |
| A unified processor architecture for RISC & VLIW DSP | 10 | 0.97 | 2005 |
| A memory-efficient realization of cyclic convolution and its application to discrete cosine transform | 17 | 1.42 | 2005 |
| A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding | 5 | 0.50 | 2005 |
| Pipelining technique for energy-aware datapaths | 0 | 0.34 | 2005 |
| Static Floating-Point Unit With Implicit Exponent Tracking For Embedded Dsp | 3 | 0.44 | 2004 |
| A Fast Dual Symbol Context-Based Arithmetic Coding For Mpeg-4 Shape Coding | 0 | 0.34 | 2004 |
| A bandwidth and memory efficient MPEG-4 shape encoder | 2 | 0.47 | 2004 |
| Optimal frame memory and data transfer scheme for MPEG-4 shape coding | 8 | 0.81 | 2004 |
| A cost-effective MPEG-4 shape-adaptive DCT with auto-aligned transpose memory organization | 6 | 0.53 | 2004 |
| Qme: An Efficient Subsampling-Based Block Matching Algorithm For Motion Estimation | 9 | 0.91 | 2004 |
| A compact DSP core with static floating-point unit & its microcode generation | 1 | 0.36 | 2004 |
| Trace-Path Analysis And Performance Estimation For Multimedia Application In Embedded System | 1 | 0.37 | 2004 |
| An Efficient VLIW DSP Architecture for Baseband Processing | 12 | 1.21 | 2003 |
| Edge-preserving texture filtering for real-time rendering | 1 | 0.37 | 2003 |
| High-speed and low-power split-radix FFT | 67 | 13.75 | 2003 |
| Performance evaluation of ring-structure register file in multimedia applications | 2 | 0.47 | 2003 |
| Generalized earliest-first fast addition algorithm | 4 | 0.56 | 2003 |
| A memory efficient realization of cyclic convolution and its application to discrete cosine transform | 8 | 0.76 | 2003 |
| Coefficient optimization for area-effective multiplier-less FIR filters | 2 | 0.50 | 2003 |
| On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture | 117 | 7.31 | 2002 |
| High-speed memory-saving architecture for the embedded block coding in JPEG2000 | 19 | 1.72 | 2002 |
| CASCADE - configurable and scalable DSP environment | 5 | 0.51 | 2002 |
| A new group distributed arithmetic design for the one dimensional discrete Fourier transform | 4 | 0.71 | 2002 |
| Index rendering: hardware-efficient architecture for 3-D graphics in multimedia system | 3 | 0.45 | 2002 |
| An efficient 2-D DWT architecture via resource cycling | 1 | 0.39 | 2001 |
| Power modeling and low-power design of content addressable memories | 23 | 2.85 | 2001 |
| Arbitrarily scalable edge-preserving interpolation for 3-D graphics and video resizing | 0 | 0.34 | 2001 |
| Improved quadratic normal vector interpolation for realistic shading | 6 | 0.54 | 2001 |
| High-Speed Booth Encoded Parallel Multiplier Design | 70 | 6.14 | 2000 |
| A high performance carry-save to signed-digit recoder for fused addition-multiplication | 1 | 0.37 | 2000 |
| Computation-effective 3-D graphics rendering architecture for embedded multimedia system | 2 | 0.47 | 2000 |
| A simple processor core design for DCT/IDCT | 36 | 3.53 | 2000 |
| On-line polygon refining using a low computation subdivision algorithm | 1 | 0.49 | 2000 |
| Deferred lighting: a computation-efficient approach for real-time 3-D graphics | 0 | 0.34 | 2000 |
| An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement | 6 | 0.83 | 1998 |
| Low-power FIR filter realization with differential coefficients and inputs | 13 | 1.53 | 1998 |
| VASS—a VLSI array system synthesizer | 3 | 0.39 | 1996 |
| A Programmable Concurrent Video Signal Processor | 1 | 0.45 | 1996 |
| Scalable array architecture design for full search block matching | 16 | 2.66 | 1995 |
| A general approach to design VLSI arrays for the multi-dimensional discrete Hartley transform | 0 | 0.34 | 1994 |
| A motion detection scheme for motion adaptive pro-scan conversion | 0 | 0.34 | 1994 |
| A novel VLSI array design for the discrete Hartley transform using cyclic convolution | 6 | 0.98 | 1994 |
