Name
Title | ||
|---|---|---|
A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals |
Abstract | ||
|---|---|---|
Sampling clock jitter degrades the dynamic range of an analog-to-digital converter (ADC). In this letter, a low-power low-noise clock signal generator for ADCs is described. As a clock signal generator, a ring-VCO-based charge pump PLL is used to reduce power dissipation within a given jitter specification. The clock signal generator is fabricated on a CMOS chip with 200-MSPS 10-bit ADC. The measured results show that the ADC keeps a 60-MHz input bandwidth and 53-dB dynamic range and a next-generation mobile wireless terminal can be realized with the ADCs and the on-chip low-power clock generator. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1093/ietfec/e91-a.2.557 | IEICE Transactions |
Keywords | Field | DocType |
dynamic range,cmos chip,clock signal generator,low-power low-noise clock signal,sampling clock jitter,jitter specification,200-msps 10-bit adc,on-chip low-power clock generator,next-generation mobile wireless terminals,53-db dynamic range,60-mhz input bandwidth,chip,pll,jitter,charge pump,power dissipation | Clock signal,Clock generator,Clock gating,Clock domain crossing,Theoretical computer science,Clock skew,Jitter,Digital clock manager,Computer hardware,Electrical engineering,CPU multiplier,Mathematics | Journal |
Volume | Issue | ISSN |
E91-A | 2 | 0916-8508 |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Akihide Sai | 1 | 20 | 8.25 |
| Daisuke Kurose | 2 | 17 | 5.11 |
| Takafumi Yamaji | 3 | 55 | 18.00 |
| Tetsuro Itakura | 4 | 187 | 33.44 |