Author Info
Name
Affiliation
Papers
AKIHIDE SAI
Toshiba Co Ltd, Ctr Corp Res & Dev, Kawasaki, Kanagawa 2128582, Japan
21
Collaborators
Citations 
PageRank 
65
20
8.25
Referers 
Referees 
References 
101
162
34
Search Limit
100162
Title
Citations
PageRank
Year
Through the Looking Glass: Diminishing Occlusions in Robot Vision Systems with Mirror Reflections00.342021
5.1 A 240×192 Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm<sup>2</sup> Voltage/Time Dual-Data-Converter-Based AFE00.342020
An Automotive LiDAR SoC for 240 × 192-Pixel 225-m-Range Imaging With a 40-Channel 0.0036-mm<sup>2</sup> Voltage/Time Dual-Data-Converter-Based AFE20.382020
Inter-Frame Smart-Accumulation Technique for Long-Range and High-Pixel Resolution LiDAR00.342019
Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits10.372019
An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators.20.382019
An 113DB-Link-Budget Bluetooth-5 SoC with an 8dBm 22%-Efficiency TX10.352018
A 15mW -105dBm Image-Sparse-Sliding-IF Receiver with Transformer-Based on-Chip Q-Enhanced RF Matching Network for a 113dB-Link-Budget BLE 5.0 TRX.00.342018
A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications00.342018
Data selection and de-noising based on reliability for long-range and high-pixel resolution LiDAR00.342018
PhaseMAC: A 14 TOPS/W 8bit GRO based Phase Domain MAC Circuit for In-Sensor-Computed Deep Learning Accelerators.00.342018
28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique.00.342017
19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC.00.342016
A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS.40.492016
26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS.20.652016
A Wide Bandwidth Analog Baseband Circuit For 60-Ghz Proximity Wireless Communication Receiver In 65-Nm Cmos00.342015
20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication70.772014
Correction to "A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication".00.342013
A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS.00.342012
A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop10.462011
A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals00.342008