Name
Abstract | ||
|---|---|---|
A compact model for the partially-depleted (PD) silicon-on- insulator (SOI) Metal Semiconductor Field Effect Transistor (MESFET) is presented. The absence of a gate-oxide makes the SOI MESFET extremely robust, able to withstand high voltages, and useful for extreme environment electronics. The device has been fabricated using a standard CMOS process. In contrast to SOI MOSFETs and GaAs MESFETs, the source-substrate voltage has a significant impact on the channel current. In this work a model has been developed that includes the effect of the buried-oxide on the performance of the MESFET. The model has been verified for a wide temperature range of -180¢陋C to 150¢陋C. A behavioral model has been included to model the breakdown voltage. The core DC and RF models have been adapted from the commercially available Triquint隆炉s Own Model (TOM3) MESFET model. A measurement-based approach is used to develop a 4-terminal device model. The charge-based approach, using S-parameter measurements was used to develop the capacitance model. We also propose a wide-temperature compensation technique by source-voltage modulation. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ISQED.2007.49 | San Jose, CA |
Keywords | DocType | Volume |
mesfet model,compact modeling,charge-based approach,breakdown voltage,4-terminal device model,soi mesfet,rf model,pd soi mesfet,soi mosfets,compact model,capacitance model,behavioral model,wide temperature designs,voltage,silicon on insulator,s parameters,robustness,temperature,cmos integrated circuits,gallium arsenide,semiconductor device modeling,gaas | Journal | 40 |
Issue | ISBN | Citations |
9 | 0-7695-2795-7 | 1 |
PageRank | References | Authors |
0.82 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Asha Balijepalli | 1 | 58 | 6.86 |
| Joseph Ervin | 2 | 1 | 0.82 |
| Yu Cao | 3 | 329 | 29.78 |
| Trevor Thornton | 4 | 3 | 1.96 |