Paper Info
Title
Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits
Abstract
This paper describes a thermal and power-supply tolerant design methodology for pipeline based circuits. It is shown that by making the circuit more tolerant to VDD and temperature (T) instability, even in the presence of process variations, a yield loss reduction is achieved. The goal is to improve signal integrity in the presence of power-supply voltage (VDD) and/or temperature (T) variations, without degrading circuit performance. By using time borrowing techniques, data integrity loss is avoided, and circuit tolerance to VDD and/or temperature variations is enhanced. The methodology is based on a Dynamic Delay Buffer (DDB) block, used to sense VDD/T variations and to induce dynamic clock skews driving a limited subset of key memory elements. Monte Carlo simulations are used to demonstrate that the proposed methodology still holds, even in the presence of process variations.
Year
DOI
Venue
2008
10.1109/DDECS.2008.4538752
DDECS
Keywords
Field
DocType
yield loss reduction,power-supply voltage,proposed methodology,power-supply tolerant design methodology,degrading circuit performance,process variation,power-supply tolerance,process tolerant design,circuit tolerance,temperature variation,signal integrity,data integrity loss,algorithm design and analysis,monte carlo simulations,digital circuits,clock skew,fault tolerance,temperature,degradation,monte carlo simulation,process design,data integrity,pipelines,monte carlo methods,design methodology
Digital electronics,Algorithm design,Computer science,Voltage,Signal integrity,Real-time computing,Electronic engineering,Data integrity,Fault tolerance,Process design,Electronic circuit
Conference
ISSN
Citations 
PageRank 
2334-3133
2
0.39
References 
Authors
6
6
Name
Order
Citations
PageRank
Jorge Semião15712.11
J. Rodriguez-Andina223730.29
Fabian Vargas317130.44
M. Santos420.39
I. Teixeira521.41
João Paulo Teixeira614022.06