Paper Info
Title
Correct modelling of nested miller compensated amplifier for discrete-time applications
Abstract
The nested Miller frequency compensation (NMC) for multistage amplifiers is a well-known technique used to overcome the phase margin degradation due the low-frequency poles introduced by cascading stages. The NMC exploits both the Miller capacitance-multiplier effect and the pole-splitting action. In literature NMC capacitor sizing rules have been presented to design amplifiers characterised by a third-order Butterworth unity-gain closed-loop response. In the paper, the Authors show these criteria neglecting transistor parasitic capacitances, may lead to incorrect amplifier behaviour when small load capacitances have to be driven. A developed model, allowing better pole location estimation, is also presented.
Year
DOI
Venue
2006
10.1007/11847083_51
PATMOS
Keywords
Field
DocType
pole location estimation,correct modelling,nested miller frequency compensation,literature nmc capacitor,developed model,multistage amplifier,nested miller,low-frequency pole,cascading stage,incorrect amplifier behaviour,miller capacitance-multiplier effect,discrete-time application,phase margin degradation,low frequency,discrete time
Capacitor,Computer science,Electronic engineering,Phase margin,Discrete time and continuous time,Transistor,Frequency compensation,Multistage amplifier,Butterworth filter,Amplifier
Conference
Volume
ISSN
ISBN
4148
0302-9743
3-540-39094-4
Citations 
PageRank 
References 
0
0.34
2
Authors
3
Name
Order
Citations
PageRank
A. Pugliese111512.90
Gregorio Cappuccino23610.11
G. Cocorullo3111.71