Name
Title | ||
|---|---|---|
Coverage directed test generation for functional verification using bayesian networks |
Abstract | ||
|---|---|---|
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or dynamic verification), by providing a new approach for Coverage Directed Test Generation (CDG). This approach is based on Bayesian networks and computer learning techniques. It provides an efficient way for closing a feedback loop from the coverage domain back to a generator that produces new stimuli to the tested design. In this paper, we show how to apply Bayesian networks to the CDG problem. Applying Bayesian networks to the CDG framework has been tested in several experiments, exhibiting encouraging results and indicating that the suggested approach can be used to achieve CDG goals. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1145/775832.775907 | DAC |
Keywords | Field | DocType |
new stimulus,suggested approach,bayesian network,hardware design cycle,dynamic verification,test generation,cdg framework,cdg goal,cdg problem,new approach,functional verification,computational modeling,hardware,logic design,hardware description languages,bayesian networks,formal verification,bayesian methods,algorithm design and analysis,feedback loop,computer networks | Bottleneck,Functional verification,Intelligent verification,Computer science,Feedback loop,Bayesian network,Artificial intelligence,High-level verification,Machine learning,Formal verification,Hardware description language | Conference |
ISSN | ISBN | Citations |
0738-100X | 1-58113-688-9 | 92 |
PageRank | References | Authors |
4.90 | 5 | 2 |