Name
Abstract | ||
|---|---|---|
Scan chains are widely used to improve the testability of integrated circuit (IC) designs and to facilitate fault diagnosis. For traditional 2D IC design, a number of design techniques have been proposed in the literature for scan-chain routing and scan-cell partitioning. However, these techniques are not effective for three-dimensional (3D) technologies, which have recently emerged as a promising means to continue technology scaling. In this article, we propose two techniques for designing scan chains in 3D ICs, with given constraints on the number of through-silicon-vias (TSVs). The first technique is based on a genetic algorithm (GA), and it addresses the ordering of cells in a single scan chain. The second optimization technique is based on integer linear programming (ILP); it addresses single-scan-chain ordering as well as the partitioning of scan flip-flops into multiple scan chains. We compare these two methods by conducting experiments on a set of ISCAS'89 benchmark circuits. The first conclusion obtained from the results is that 3D scan-chain optimization achieves significant wire-length reduction compared to 2D counterparts. The second conclusion is that the ILP-based technique provides lower bounds on the scan-chain interconnect length for 3D ICs, and it offers considerable reduction in wire-length compared to the GA-based heuristic method. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1145/1543438.1543442 | JETC |
Keywords | Field | DocType |
scan-chain routing,optimization technique,lp relaxation,significant wire-length reduction,genetic algorithm,design technique,randomized rounding,general terms: algorithms additional key words and phrases: 3d ics,scan-chain design,considerable reduction,ga-based heuristic method,scan-chain optimization,integer linear programming,three-dimensional integrated circuit,ic design,scan-cell partitioning,ilp-based technique,integrated circuit,three dimensional,lower bound,through silicon via | Testability,Heuristic,Computer science,Scan chain,Algorithm,Electronic engineering,Integrated circuit design,Randomized rounding,Integer programming,Integrated circuit,Genetic algorithm | Journal |
Volume | Issue | ISSN |
5 | 2 | 1550-4832 |
Citations | PageRank | References |
20 | 1.42 | 20 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaoxia Wu | 1 | 535 | 38.61 |
| Paul Falkenstern | 2 | 84 | 5.25 |
| K Chakrabarty | 3 | 8173 | 636.14 |
| Yuan Xie | 4 | 6430 | 407.00 |