Name
Abstract | ||
|---|---|---|
In order to harness the full compute power of many-core processors, future designs must focus on effective utilization of on-chip cache and bandwidth resources. In this paper, we address the dual goals of (1) reducing on-chip communication overheads and (2) improving on-chip cache space utilization resulting in larger effective cache capacity and thereby potentially reduced off-chip traffic.We present a new cache coherence protocol that decouples the logical binding between data and metadata in a cache set. This decoupling allows data and metadata for a cache line to be independently delegated to any location on chip. By delegating metadata to the current owner/modifier of a cache line, communication overhead for metadata maintenance is avoided and communication can be effectively localized between interacting processes.By decoupling metadata from data, data space in the cache can be more efficiently utilized by avoiding unnecessary data replication. Using full system simulation, we demonstrate that our decoupled protocol achieves an average (geometric mean) speedup of 1.24 (1.3 with microbenchmarks) compared to a base statically mapped directory-based non-uniform cache access protocol, while generating only 65% and 74% of the on-chip and off-chip traffic respectively, and consuming 74% of the corresponding energy (95% of the power) in the on-chip memory and interconnect compared to the base system. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/PACT.2009.24 | PACT |
Keywords | Field | DocType |
delegable cache,cache line,new cache coherence protocol,off-chip traffic,chip multiprocessors,cache set,on-chip cache,decoupling metadata,decoupled cache,non-uniform cache access protocol,delegable cache data,on-chip cache space utilization,ddcache,larger effective cache capacity,-cache coherence,data space,protocols,coherence,data mining,chip,cache coherence,system on a chip,col,meta data,data replication,geometric mean | Cache invalidation,Cache pollution,Computer science,Cache,MESI protocol,Parallel computing,Cache algorithms,Page cache,Real-time computing,Cache coloring,Smart Cache | Conference |
ISSN | Citations | PageRank |
1089-795X | 7 | 0.45 |
References | Authors | |
31 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hemayet Hossain | 1 | 59 | 3.09 |
| Sandhya Dwarkadas | 2 | 3504 | 257.31 |
| Michael C. Huang | 3 | 875 | 58.47 |