Name
Papers
Collaborators
SANDHYA DWARKADAS
95
123
Citations 
PageRank 
Referers 
3504
257.31
5899
Referees 
References 
1880
1507
Search Limit
1001000
Title
Citations
PageRank
Year
Interference-aware Micro-architectural Resource Manager for Hybrid Workloads.00.342021
Performance Characterization Of Htap Workloads00.342021
TimeCache: Using Time to Eliminate Cache Side Channels when Sharing Software00.342021
On the Impact of Instruction Address Translation Overhead10.342019
Managing application parallelism via parallel efficiency regulation - poster.00.342019
Top Picks in Computer Architecture from Conferences in 2018.00.342019
2018 Maurice Wilkes Award Given to Gabriel Loh.00.342018
Shared address translation revisited.50.422016
Coherence Stalls or Latency Tolerance: Informed CPU Scheduling for Socket and Core Sharing.40.472016
Introduction to the Special Issue on PPoPP'14.00.342016
Data sharing or resource contention: toward performance transparency on multicore systems50.482015
Characterization of Shared Library Access Patterns of Android Applications00.342015
Power containers: an OS facility for fine-grained power and energy management on multicore servers270.822013
An Application-Tailored Approach to Hardware Cache Coherence00.342013
Protozoa: adaptive granularity cache coherence90.452013
Verifying safety and liveness for the FlexTM hybrid transactional memory20.392013
Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy170.702012
A Flexible Framework for Throttling-Enabled Multicore Management (TEMM)130.542012
Power and energy containers for multicore servers30.402012
SPATL: Honey, I Shrunk the Coherence Directory300.792011
Analyzing Conflicts in Hardware-Supported Memory Transactions10.362011
Hierarchical parallelization of gene differential association analysis.80.342011
POPS: Coherence Protocol Optimization for Both Private and Shared Data260.832011
Implementation tradeoffs in the design of flexible transactional memory support70.452010
An evaluation of per-chip nonuniform frequency scaling on multicores110.532010
SPACE: sharing pattern-based directory coherence for multicore scalability310.902010
Sentry: light-weight auxiliary memory access control50.472010
Hardware execution throttling for multi-core resource management271.002009
DDCache: Decoupled and Delegable Cache Data and Metadata70.452009
Towards practical page coloring-based multicore cache management1324.002009
Tapping into parallelism with transactional memory10.362009
Refereeing conflicts in hardware transactional memory281.132009
Improving support for locality and fine-grain sharing in chip multiprocessors190.812008
Alert-on-update: a communication aid for shared memory multiprocessors50.592007
Nonblocking transactions without indirection using alert-on-update151.172007
Analysis of input-dependent program behavior using active profiling30.392007
Processor hardware counter statistics as a first-class system resource332.762007
Program phase detection and exploitation70.542006
Compatible phase co-scheduling on a CMP of multi-threaded processors371.642006
Low traffic overlay networks with large routing tables170.812005
Shared memory computing on clusters with symmetric multiprocessors and system area networks70.522005
Partitioning Multi-Threaded Processors with a Large Number of Threads141.042005
On scaling latent semantic indexing for large peer-to-peer systems452.352004
Profile-Driven Component Placement for Cluster-Based Online Services90.872004
Parallel Metropolis coupled Markov chain Monte Carlo for Bayesian phylogenetic inference.394.402004
Hybrid global-local indexing for effcient peer-to-peer information retrieval792.522004
Integrating Remote Invocation and Distributed Shared State110.782004
Hot-and-Cold: using criticality in the design of energy-efficient caches60.502003
Characterizing and Predicting Program Behavior and its Variability1207.102003
Garbage collector assisted memory offloading for memory-constrained devices20.412003
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