Name
Abstract | ||
|---|---|---|
This paper describes a new circuit technique for designing noise-tolerant dynamic logic. It is shown that voltage scaling aggravates the crosstalk noise problem and reduces circuit noise immunity, motivating the need for noise-tolerant circuit design. In a 0.35-/spl mu/m CMOS technology and at a given supply voltage, the proposed technique provides an improvement in noise immunity of 1.8/spl times... |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/4.902768 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Circuit noise,Crosstalk,Dynamic voltage scaling,CMOS technology,CMOS logic circuits,Logic design,Logic circuits,Noise reduction,Circuit synthesis,Adders | Journal | 36 |
Issue | ISSN | Citations |
2 | 0018-9200 | 25 |
PageRank | References | Authors |
3.48 | 8 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ganesh Balamurugan | 1 | 144 | 20.77 |
| Naresh R. Shanbhag | 2 | 2027 | 205.25 |