Paper Info
Title
Increasing Fault Tolerance to Multiple Upsets Using Digital Sigma-Delta Modulators
Abstract
As the transistor gate length goes straightforward to the sub-micron dimension, there is an increased possibility of occurrence of external interferences in these devices. The direct effect of such external and/or intrinsic interferences is, in many cases, the total mismatch between the desired answer of the system and the obtained response. So, new techniques must be studied in order to guarantee the correct operation of these systems, under multiple simultaneous faults. This work presents the use of a totally digital sigma-delta modulator that is used to develop arithmetic operations with much better results than if a common digital operator was used. Simulations results show that, even under multiple simultaneous faults, the system presents very good results, as in the addition case, where a maximum standard deviation of 0.7 is achieved for sigma-delta-modulated signals, while for the digital adder alone, this value is 57.5. Such behavior is good enough to be used in operators that tolerate small errors, like in the digital filters where these errors are embedded in the system noise.
Year
DOI
Venue
2005
10.1109/IOLTS.2005.37
IOLTS
Keywords
Field
DocType
fault tolerance,common digital operator,system noise,digital sigma-delta modulator,digital sigma-delta modulators,addition case,multiple simultaneous fault,external interference,arithmetic operation,digital filter,digital adder,good result,redundancy,signal processing,standard deviation,interference,fault tolerant,embedded systems,delta sigma modulation,adders,sigma delta modulator
Signal processing,Digital filter,Adder,Computer science,Real-time computing,Electronic engineering,Delta-sigma modulation,Modulation,Redundancy (engineering),Fault tolerance,Single event upset
Conference
ISBN
Citations 
PageRank 
0-7695-2406-0
4
0.49
References 
Authors
1
2
Name
Order
Citations
PageRank
Erik Schuler1184.83
Luigi Carro21393166.42