Title
A 10-Gb/S Two-Dimensional Eye-Opening Monitor In 0.13-Mu M Standard Cmos
Abstract
An eye-opening monitor (EOM) architecture that can capture a two-dimensional (2-D) map of the eye diagram of a highspeed data signal has been developed. Two single-quadrant phase rotators and one digital-to-analog converter (DAC) are used to generate rectangular masks with variable sizes and aspect ratios. Each mask is overlapped with the received eye diagram and the number of signal transitions inside the mask is recorded as error. The combination of rectangular masks with the same error creates error contours that overall provide a 2-D map of the eye. The authors have implemented a prototype circuit in 0.13-mu m standard CMOS technology that operates up to 12.5 Gb/s at 1.2-V supply. The EOM maps the input eye to a 2-D error diagram with tip to 68-dB mask error dynamic range. The left and right halves of the eyes are monitored separately to capture horizontally asymmetric eyes. The chip consumes 330 mW and operates reliably with supply voltages as low as 1 V at 10 Gb/s. The authors also present a detailed analysis that verifies if the measurements are in good agreement with the expected results.
Year
DOI
Venue
2005
10.1109/JSSC.2005.856576
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Keywords
DocType
Volume
bit error rate, CMOS, eye diagram, eye monitor, eye-opening monitor, high speed, mask error rate, signal quality
Journal
40
Issue
ISSN
Citations 
12
0018-9200
26
PageRank 
References 
Authors
2.56
5
5
Name
Order
Citations
PageRank
Behnam Analui1639.80
Alexander Rylyakov213423.32
Sergey V. Rylov315919.94
Mounir Meghelli47814.76
Ali Hajimiri57310.48