Name
Abstract | ||
|---|---|---|
The paper describes an embedded circuit for the single shot jitter measurement of the clock signal. Based on a jitter amplified technique with a pulse removing mechanism, the pico-second level resolution is achieved in the wide frequency range. In addition, a gain-locked loop calibration scheme is proposed to keep the amplification ratio constant under PVT variations. Fabricated by 0.13-um CMOS process, the tested circuit can achieve a resolution of 2 ps root mean square (rms) jitter at an input range from few tens of megahertz to 1.6 GHz. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/DATE.2010.5457074 | DATE |
Keywords | Field | DocType |
cmos process,cmos integrated circuits,wide frequency range,calibration,gain-locked loop calibration,jitter,time measurement,amplification ratio,clock signal,input range,gain-locked loop calibration scheme,clocks,pico-second level resolution,pvt variation,embedded wide-range,embedded circuit,single shot jitter measurement,high-resolution clock jitter measurement,clock jitter measurement circuit,size 0.13 mum,picosecond level resolution,root mean square,tested circuit,mean square error methods,high resolution,topology,frequency,temperature measurement,deadlock,design for testability,voltage | Clock signal,Computer science,Cmos process,Real-time computing,CMOS,Electronic engineering,Pulse (signal processing),Root mean square,Jitter,Temperature measurement,Calibration | Conference |
ISSN | ISBN | Citations |
1530-1591 | 978-1-4244-7054-9 | 0 |
PageRank | References | Authors |
0.34 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yu Lee | 1 | 11 | 3.21 |
| Ching-Yuan Yang | 2 | 227 | 36.15 |
| Nai-Chen Daniel Cheng | 3 | 2 | 1.40 |
| Ji-Jan Chen | 4 | 116 | 9.34 |