Name
Title | ||
|---|---|---|
Methodology for analysis of TSV stress induced transistor variation and circuit performance |
Abstract | ||
|---|---|---|
As continued scaling becomes increasingly difficult, 3D integration with through silicon vias (TSVs) has emerged as a viable solution to achieve higher bandwidth and power efficiency. Mechanical stress induced by thermal mismatch between TSVs and the silicon bulk arising during wafer fabrication and 3D integration, is a key constraint. In this work, we propose a complete flow to characterize the influence of TSV stress on transistor and circuit performance. First, we analyze the thermal stress contour near the silicon surface with single and multiple TSVs through both finite element analysis (FEA) and linear superposition methods. Then, the biaxial stress is converted to mobility and threshold voltage variations depending on transistor type and geometric relation between TSVs and transistors. Next, we propose an efficient algorithm to calculate circuit variation corresponding to TSV stress based on a grid partition approach. Finally, we discuss a TSV pattern optimization strategy, and employ a series of 17-stage ring oscillators using 40 nm CMOS technology as a test case for the proposed approach. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISQED.2012.6187497 | ISQED |
Keywords | Field | DocType |
optimisation,circuit variation calculation,cmos integrated circuits,biaxial stress conversion,integrated circuit testing,mechanical stress,fea,thermal stress contour analysis,three-dimensional integrated circuits,size 40 nm,wafer fabrication,through silicon vias,17-stage ring oscillator,cmos technology,linear superposition method,tsv pattern optimization strategy,mobility voltage variation,finite element analysis,grid partition approach,circuit performance,threshold voltage variation,mosfet,oscillators,tsv stress induced transistor variation analysis,thermal mismatch,3d integration,geometric relation,finite element methods,through silicon via,thermal stress,power efficiency,stress,threshold voltage,layout,silicon,transistors,ring oscillator | Electrical efficiency,Computer science,Wafer fabrication,CMOS,Finite element method,Stress (mechanics),Electronic engineering,MOSFET,Transistor,Threshold voltage | Conference |
ISSN | ISBN | Citations |
1948-3287 | 978-1-4673-1034-5 | 6 |
PageRank | References | Authors |
0.64 | 1 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Li Yu | 1 | 144 | 25.48 |
| Wen-Yao Chang | 2 | 13 | 2.48 |
| Kewei Zuo | 3 | 8 | 1.05 |
| Jean Wang | 4 | 6 | 0.64 |
| Douglas Yu | 5 | 10 | 2.37 |
| Duane Boning | 6 | 201 | 49.37 |