Name
Abstract | ||
|---|---|---|
In this paper, a novel diagnosis method is proposed. The proposed technique uses machine learning techniques instead of traditional cause-effect and/or effect-cause analysis. The proposed technique has several advantages over traditional diagnosis methods, especially for volume diagnosis. In the proposed method, since the time consuming diagnosis process is reduced to merely evaluating several decision functions, run time complexity is much lower than traditional diagnosis methods. The proposed technique can provide not only high resolution diagnosis but also statistical data by classifying defective chips according to locations of their defects. Even with highly compressed output responses, the proposed diagnosis technique can correctly locate defect locations for most defective chips. The proposed technique correctly located defects for more than 90% (86%) defective chips at 50times (100times) output compaction. Run time for diagnosing a single simulated defect chip was only tens of milli-seconds. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/DATE.2009.5090792 | DATE |
Keywords | Field | DocType |
machine learning-based volume diagnosis,integrated circuit testing,proposed technique,proposed diagnosis technique,time complexity,run time complexity,high resolution diagnosis,novel diagnosis method,soc,statistical analysis,learning (artificial intelligence),traditional diagnosis method,system-on-chip,single simulated defect chip diagnosis,fault diagnosis,support vector machine,defective chip classification,statistical data,semiconductor companies,volume diagnosis,time consuming diagnosis process,highly compressed output response,defective chip,support vector machines,semiconductor industry,electronic engineering computing,defect localization,inspection,learning artificial intelligence,system testing,polynomials,hardware description language,high resolution,chip,national electric code,simulation,system on chip,compaction,vhdl,machine learning | System on a chip,Computer science,System testing,Support vector machine,Chip,Artificial intelligence,VHDL,Time complexity,National Electrical Code,Machine learning,Built-in self-test | Conference |
ISSN | ISBN | Citations |
1530-1591 | 978-1-4244-3781-8 | 10 |
PageRank | References | Authors |
0.55 | 14 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seongmoon Wang | 1 | 605 | 48.50 |
| Wenlong Wei | 2 | 81 | 6.50 |