Name
Title | ||
|---|---|---|
A self-driven test structure for pseudorandom testing of non-scan sequential circuits |
Abstract | ||
|---|---|---|
Introduced is a self-driven test point structure which permits at-speed, on-chip, non-scan, sequential testing using parallel pseudorandom test patterns applied only to the primary inputs of the circuit under test. The test network is unique in that aside from a test mode flag, all I/O signals needed for test system operation are tapped from within the circuit itself. High single stuck-at fault coverage is achieved for a number of ISCAS-89 benchmarks. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/VTEST.1996.510830 | VTS |
Keywords | Field | DocType |
test system operation,pseudorandom testing,high single stuck-at fault,iscas-89 benchmarks,parallel pseudorandom test pattern,self-driven test point structure,sequential testing,test network,self-driven test structure,non-scan sequential circuit,primary input,test mode flag,sequential circuits,fault coverage,chip,design for testability | Design for testing,Automatic test pattern generation,Sequential logic,Fault coverage,Computer science,Algorithm,Electronic engineering,Real-time computing,Test compression,Sequential analysis,Built-in self-test,Pseudorandom number generator | Conference |
ISBN | Citations | PageRank |
0-8186-7304-4 | 3 | 0.55 |
References | Authors | |
9 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| F. Muradali | 1 | 98 | 10.94 |
| J. Rajski | 2 | 985 | 63.36 |