Paper Info
Title
Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms
Abstract
In an SoC, building local storage in each accelerator is area inefficient due to the low average utilization. In this paper, we present design and implementation of Buffer-integrated-Caching (BiC), which allows many buffers to be instantiated simultaneously in caches. BiC enables cores to view portions of the SRAM as cache while accelerators access other portions of the SRAM as private buffers. We demonstrate the cost-effectiveness of BiC based on a recognition MPSoC that includes two PentiumTM cores, an Augmented Reality accelerator and a speech recognition accelerator. With 3% extra area added to the baseline L2 cache, BiC eliminates the need to build 215KB dedicated SRAM for the accelerators, while increasing total cache misses by no more than 0.3%.
Year
DOI
Venue
2011
10.1145/2024724.2024938
DAC
Keywords
Field
DocType
baseline l2 cache,accelerators access,local storage,recognition mpsoc,total cache,dedicated sram,cost-effective sram architecture,extra area,speech recognition accelerator,embedded platform,pentiumtm core,augmented reality accelerator,indexation,indexes,cost effectiveness,hardware,system on a chip,speech recognition,memory,augmented reality,cache memory,l2 cache,cache,system on chip
System on a chip,Cache,Computer science,CPU cache,Static random-access memory,Augmented reality,Mobile device,Software,MPSoC,Embedded system
Conference
ISSN
ISBN
Citations 
0738-100X
978-1-4503-0636-2
10
PageRank 
References 
Authors
0.61
17
6
Name
Order
Citations
PageRank
Carlos Flores Fajardo1161.50
Zhen Fang2917.62
Ravishankar K. Iyer3111975.72
German Fabila Garcia4121.31
Seung Eun Lee522422.34
Li Zhao660434.84