Abstract | ||
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We address the problem of rectifying an erroneous combinational circuit. Based on the symbolic binary decision diagram techniques, we consider the rectification process as a sequence of partial corrections. Each partial correction reduces the size of the input vector set that produces error responses. Compared with the existing approaches, this approach is more general, and thus, suitable for circuits with multiple errors and for the engineering change problem. Also, we derive the necessary and sufficient condition of general single-gate correction to improve the quality of rectification. To handle larger circuits, we develop a hybrid approach that makes use of the information of structural correspondence between specification and implementation. Experiments are performed on a suite of industrial examples as well as the entire set of ISCAS'85 benchmark circuits to demonstrate its effectiveness |
Year | DOI | Venue |
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1999 | 10.1109/43.784128 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
single-gate correction,symbolic binary decision diagram techniques,integrated circuit testing,general single-gate correction,logic CAD,combinational circuits,hybrid tool,partial correction,binary decision diagrams,input vector set,structural correspondence,hybrid approach,ISCAS'85 benchmark circuits,symbol manipulation,error responses,existing approach,index terms— circuit synthesis,engineering change problem,automatic logic rectification,partial corrections,erroneous combinational circuit,AutoFix,benchmark circuit,circuit CAD,design automation,automatic testing,entire set,rectification process,symbol manipulation.,error correction,multiple errors | Journal | 18 |
Issue | ISSN | Citations |
9 | 0278-0070 | 18 |
PageRank | References | Authors |
1.19 | 30 | 3 |
Name | Order | Citations | PageRank |
---|---|---|---|
Shi-Yu Huang | 1 | 766 | 70.53 |
Kuang-chien Chen | 2 | 347 | 30.84 |
Kwang-Ting Cheng | 3 | 5755 | 513.90 |