Name
Abstract | ||
|---|---|---|
Constraining and biasing are frequently used techniques toenhance the quality of randomized vector generation. In this paper,we present a novel method that combines constraints and input biasingin automatic bit-vector generation for block-level functionalverification of digital designs, which is implemented in a toolcalled SimGen. Vector generation in SimGen is confined to a legalinput space that is defined by constraints symbolically representedin Binary Decision Diagrams (BDDs). A constraint involving statevariables in the design defines a state-dependent legal input space.Input biasing can also depend on the state of the design. The effectof constraints and input biasing are combined to form what we calledthe constrained probabilities of input vectors. An algorithm isdeveloped to efficiently generate input vectors on-the-fly duringsimulation. The vector generation is a one-pass process, i.e., nobacktracking or retry is needed. Also, we describe methods ofminimizing the constraint BDDs in an effort to reduce thesimulation-time overhead of SimGen. Furthermore we discuss theapplication of SimGen to a set of commercial design blocks. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1023/A:1008301108750 | J. Electronic Testing |
Keywords | DocType | Volume |
vector generation,constraint,biasing,probability,BDD,partitioning | Journal | 16 |
Issue | ISSN | Citations |
1-2 | 1573-0727 | 2 |
PageRank | References | Authors |
0.62 | 17 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jun Yuan | 1 | 2 | 0.62 |
| Kurt Shultz | 2 | 14 | 2.18 |
| Carl Pixley | 3 | 418 | 44.09 |
| Hillel Miller | 4 | 2 | 0.62 |
| Adnan Aziz | 5 | 1778 | 149.76 |